ep點穿孔技術是什麼意思

❶ 璐寸墖浜屾瀬綆″嵃瀛桬P,灝佽呭艦寮忔槸浠涔

銆銆褰㈠紡錛
銆銆DIP灝佽

銆銆70騫翠唬嫻佽岀殑鏄鍙屽垪鐩存彃灝佽咃紝綆縐癉IP(Dual In-line Package)銆侱IP灝佽呯粨鏋勫叿鏈変互涓嬬壒鐐:
銆銆1.閫傚悎PCB鐨勭┛瀛斿畨瑁;
銆銆2.姣擳O鍨嬪皝瑁(鍥1)鏄撲簬瀵筆CB甯冪嚎;
銆銆3.鎿嶄綔鏂逛究銆
銆銆DIP灝佽呯粨鏋勫艦寮忔湁:澶氬眰闄剁摲鍙屽垪鐩存彃寮廌IP錛屽崟灞傞櫠鐡峰弻鍒楃洿鎻掑紡DIP錛屽紩綰挎嗘灦寮廌IP(鍚鐜葷拑闄剁摲灝佹帴寮忥紝濉戞枡鍖呭皝緇撴瀯寮忥紝闄剁摲浣庣啍鐜葷拑灝佽呭紡)錛屽傚浘2鎵紺恆
銆銆琛￠噺涓涓鑺鐗囧皝瑁呮妧鏈鍏堣繘涓庡惁鐨勯噸瑕佹寚鏍囨槸鑺鐗囬潰縐涓庡皝瑁呴潰縐涔嬫瘮錛岃繖涓姣斿艱秺鎺ヨ繎1瓚婂ソ銆備互閲囩敤40鏍笽/O寮曡剼濉戞枡鍖呭皝鍙屽垪鐩存彃寮忓皝瑁(PDIP)鐨凜PU涓轟緥錛屽叾鑺鐗囬潰縐/灝佽呴潰縐=3脳3/15.24脳50=1錛86,紱1鐩稿樊寰堣繙銆備笉宸鐗╀箮闅劇湅鍑猴紝榪欑嶅皝瑁呭昂瀵歌繙姣旇姱鐗囧ぇ錛岃存槑灝佽呮晥鐜囧緢浣庯紝鍗犲幓浜嗗緢澶氭湁鏁堝畨瑁呴潰鋩傚嚡縐銆
銆銆Intel鍏鍙歌繖鏈熼棿鐨凜PU濡8086銆80286閮介噰鐢≒DIP灝佽呫
銆銆鑺鐗囪澆浣撳皝瑁

銆銆80騫翠唬鍑虹幇浜嗚姱鐗囪澆浣撳皝瑁咃紝鍏朵腑鏈夐櫠鐡鋒棤寮曠嚎鑺鐗囪澆浣揕CCC(Leadless Ceramic Chip Carrier)銆佸戞枡鏈夊紩綰胯姱鐗囪澆浣揚LCC(Plastic Leaded Chip Carrier)銆佸皬灝哄稿皝瑁匰OP(Small Outline Package)銆佸戞枡鍥涜竟寮曞嚭鎵佸鉤灝佽匬QFP(Plastic Quad Flat Package)錛屽皝瑁呯粨鏋勫艦寮忓傚浘3銆佸浘4鍜屽浘5鎵紺恆
銆銆浠0.5mm鐒婂尯涓蹇冭窛錛208鏍笽/O寮曡剼鐨凲FP灝佽呯殑CPU涓轟緥錛屽栧艦灝哄28脳28mm錛岃姱鐗囧昂瀵10脳10mm錛屽垯鑺鐗囬潰縐/灝佽呴潰縐=10脳10/28脳28=1錛7.8錛岀敱姝ゅ彲瑙丵FP姣擠IP鐨勫皝瑁呭昂瀵稿ぇ澶у噺灝忋俀FP鐨勭壒鐐規槸:
銆銆1.閫傚悎鐢⊿MT琛ㄩ潰瀹夎呮妧鏈鍦≒CB涓婂畨瑁呭竷綰;
銆銆2.灝佽呭栧艦灝哄稿皬錛屽瘎鐢熷弬鏁板噺灝忥紝閫傚悎楂橀戝簲鐢;
銆銆3.鎿嶄綔鏂逛究;
銆銆4.鍙闈犳ч珮銆
銆銆鍦ㄨ繖鏈熼棿錛孖ntel鍏鍙哥殑CPU錛屽Intel 80386灝遍噰鐢ㄥ戞枡鍥涜竟寮曞嚭鎵佸鉤灝佽匬QFP銆
銆銆BGA灝佽

銆銆90騫翠唬闅忕潃闆嗘垚鎶鏈鐨勮繘姝ャ佽懼囩殑鏀硅繘鍜屾繁浜氬井綾蟲妧鏈鐨勪嬌鐢錛孡SI銆乂LSI銆乁LSI鐩哥戶鍑虹幇錛岀呭崟鑺鐗囬泦鎴愬害涓嶆柇鎻愰珮錛屽歸泦鎴愮數璺灝佽呰佹眰鏇村姞涓ユ牸錛孖/O寮曡剼鏁版ュ墽澧炲姞錛屽姛鑰椾篃闅忎箣澧炲ぇ銆備負婊¤凍鍙戝睍鐨勯渶瑕侊紝鍦ㄥ師鏈夊皝瑁呭搧縐嶅熀紜涓婏紝鍙堝炴坊浜嗘柊鐨勫搧縐嶁斺旂悆鏍呴樀鍒楀皝瑁咃紝綆縐癇GA(Ball Grid Array Package)銆
銆銆BGA涓鍑虹幇渚挎垚涓篊PU銆佸崡鍖楁ˉ絳塚LSI鑺鐗囩殑楂樺瘑搴︺侀珮鎬ц兘銆佸氬姛鑳藉強楂業/O寮曡剼灝佽呯殑鏈浣抽夋嫨銆傚叾鐗圭偣鏈:
銆銆1.I/O寮曡剼鏁拌櫧鐒跺炲氾紝浣嗗紩鑴氶棿璺濊繙澶т簬QFP錛屼粠鑰屾彁楂樹簡緇勮呮垚鍝佺巼;
銆銆2.鉶界劧瀹冪殑鍔熻楀炲姞錛屼絾BGA鑳界敤鍙鎺у岄櫡鑺鐗囨硶鐒婃帴錛岀畝縐癈4鐒婃帴錛屼粠鑰屽彲浠ユ敼鍠勫畠鐨勭數鐑鎬ц兘:
銆銆3.鍘氬害姣擰FP鍑忓皯1/2浠ヤ笂錛岄噸閲忓噺杞3/4浠ヤ笂;
銆銆4.瀵勭敓鍙傛暟鍑忓皬錛屼俊鍙蜂紶杈撳歡榪熷皬錛屼嬌鐢ㄩ戠巼澶уぇ鎻愰珮;
銆銆5.緇勮呭彲鐢ㄥ叡闈㈢剨鎺ワ紝鍙闈犳ч珮;
銆銆6.BGA灝佽呬粛涓嶲FP銆丳GA涓鏍鳳紝鍗犵敤鍩烘澘闈㈢Н榪囧ぇ;
銆銆Intel鍏鍙稿硅繖縐嶉泦鎴愬害寰堥珮(鍗曡姱鐗囬噷杈300涓囧彧浠ヤ笂鏅朵綋綆)錛屽姛鑰楀緢澶х殑CPU鑺鐗囷紝濡侾entium銆丳entium Pro銆丳entium 鈪￠噰鐢ㄩ櫠鐡烽拡鏍呴樀鍒楀皝瑁匔PGA鍜岄櫠鐡風悆鏍呴樀鍒楀皝瑁匔BGA錛屽苟鍦ㄥ栧３涓婂畨瑁呭井鍨嬫帓椋庢墖鏁ｇ儹錛屼粠鑰岃揪鍒扮數璺鐨勭ǔ瀹氬彲闈犲伐浣溿
銆銆闈㈠悜鏈鏉ョ殑鏂扮殑灝佽呮妧鏈

銆銆BGA灝佽呮瘮QFP鍏堣繘錛屾洿姣擯GA濂斤紝浣嗗畠鐨勮姱鐗囬潰縐/灝佽呴潰縐鐨勬瘮鍊間粛寰堜綆銆
銆銆Tessera鍏鍙稿湪BGA鍩虹涓婂仛浜嗘敼榪涳紝鐮斿埗鍑哄彟涓縐嶇О涓何糂GA鐨勫皝瑁呮妧鏈錛屾寜0.5mm鐒婂尯涓蹇冭窛錛岃姱鐗囬潰縐/灝佽呴潰縐鐨勬瘮涓1:4錛屾瘮BGA鍓嶈繘浜嗕竴澶фャ
銆銆1994騫9鏈堟棩鏈涓夎櫄鎮夎彵鐢墊皵鐮旂┒鍑轟竴縐嶈姱鐗囬潰縐/灝佽呴潰縐=1:1.1鐨勫皝瑁呯粨鏋勶紝鍏跺皝瑁呭栧艦灝哄稿彧姣旇８鑺鐗囧ぇ涓鐐圭偣銆備篃灝辨槸璇達紝鍗曚釜IC鑺鐗鏈夊氬ぇ錛屽皝瑁呭昂瀵稿氨鏈夊氬ぇ錛屼粠鑰岃癁鐢熶簡涓縐嶆柊鐨勫皝瑁呭艦寮忥紝鍛藉悕涓鴻姱鐗囧昂瀵稿皝瑁咃紝綆縐癈SP(Chip Size Package鎴朇hip Scale Package)銆CSP灝佽鍏鋒湁浠ヤ笅鐗圭偣:
銆銆1.婊¤凍浜哃SI鑺鐗囧紩鍑鴻剼涓嶆柇澧炲姞鐨勯渶瑕;
銆銆2.瑙ｅ喅浜咺C瑁歌姱鐗囦笉鑳借繘琛屼氦嫻佸弬鏁版祴璇曞拰鑰佸寲絳涢夌殑闂棰;
銆銆3.灝佽呴潰縐緙╁皬鍒癇GA鐨1/4鑷1/10錛屽歡榪熸椂闂寸緝灝忓埌鏋佺煭銆
銆銆鏇炬湁浜烘兂錛屽綋鍗曡姱鐗囦竴鏃惰繕杈句笉鍒板氱嶈姱鐗囩殑闆嗘垚搴︽椂錛岃兘鍚﹀皢楂橀泦鎴愬害銆侀珮鎬ц兘銆侀珮鍙闈犵殑CSP鑺鐗(鐢↙SI鎴朓C)鍜屼笓鐢ㄩ泦鎴愮數璺鑺鐗(ASIC)鍦ㄩ珮瀵嗗害澶氬眰浜掕仈鍩烘澘涓婄敤琛ㄩ潰瀹夎呮妧鏈(SMT)緇勮呮垚涓哄氱嶅氭牱鐢靛瓙緇勪歡銆佸瓙緋葷粺鎴栫郴緇熴傜敱榪欑嶆兂娉曚駭鐢熷嚭澶氳姱鐗囩粍浠禡CM(Multi Chip Model)銆傚畠灝嗗圭幇浠ｅ寲鐨勮＄畻鏈恆佽嚜鍔ㄥ寲銆侀氳涓氱瓑棰嗗煙浜х敓閲嶅ぇ褰卞搷銆侻CM鐨勭壒鐐規湁:
銆銆1.灝佽呭歡榪熸椂闂寸緝灝忥紝鏄撲簬瀹炵幇緇勪歡楂橀熷寲;
銆銆2.緙╁皬鏁存満/緇勪歡灝佽呭昂瀵稿拰閲嶉噺錛屼竴鑸浣撶Н鍑忓皬1/4錛岄噸閲忓噺杞1/3;
銆銆3.鍙闈犳уぇ澶ф彁楂樸
銆銆闅忕潃LSI璁捐℃妧鏈鍜屽伐鑹虹殑榪涙ュ強娣變簹寰綾蟲妧鏈鍜屽井緇嗗寲緙灝忚姱鐗灝哄哥瓑鎶鏈鐨勪嬌鐢錛屼漢浠浜х敓浜嗗皢澶氫釜LSI鑺鐗囩粍瑁呭湪涓涓綺懼瘑澶氬眰甯冪嚎鐨勫栧３鍐呭艦鎴怣CM浜у搧鐨勬兂娉曘傝繘涓姝ュ張浜х敓鍙︿竴縐嶆兂娉:鎶婂氱嶈姱鐗囩殑鐢佃礬闆嗘垚鍦ㄤ竴涓澶у渾鐗囦笂錛屼粠鑰屽張瀵艱嚧浜嗗皝瑁呯敱鍗曚釜灝忚姱鐗囩駭杞鍚戠呭渾鐗囩駭(wafer level)灝佽呯殑鍙橀潻錛岀敱姝ゅ紩鍑虹郴緇熺駭鑺鐗嘢OC(System On Chip)鍜岀數鑴戠駭鑺鐗嘝COC(PC On Chip)銆
銆銆闅忕潃CPU鍜屽叾浠朥LSI鐢佃礬鐨勮繘姝ワ紝闆嗘垚鐢佃礬鐨勫皝瑁呭艦寮忎篃灝嗘湁鐩稿簲鐨勫彂灞曪紝鑰屽皝瑁呭艦寮忕殑榪涙ュ張灝嗗弽榪囨潵淇冩垚鑺鐗囨妧鏈鍚戝墠鍙戝睍銆
銆銆灝佽呭艦寮忔槸鎸囧畨瑁呭崐瀵間綋闆嗘垚鐢佃礬鑺鐗囩敤鐨勫栧３銆傚畠涓嶄粎璧風潃瀹夎呫佸滻瀹氥佸瘑灝併佷繚鎶よ姱鐗囧強澧炲己鐢電儹鎬ц兘絳夋柟闈㈢殑浣滅敤錛岃屼笖榪橀氳繃鑺鐗囦笂鐨勬帴鐐圭敤瀵肩嚎榪炴帴鍒板皝瑁呭栧３鐨勫紩鑴氫笂錛岃繖浜涘紩鑴氬張閫氳繃鍗板埛鐢佃礬鏉涓婄殑瀵肩嚎涓庡叾浠栧櫒浠剁浉榪炴帴銆傝閲忎竴涓鑺鐗囧皝瑁呮妧鏈鍏堣繘涓庡惁鐨勯噸瑕佹寚鏍囨槸鑺鐗囬潰縐涓庡皝瑁呴潰縐涔嬫瘮錛岃繖涓姣斿艱秺鎺ヨ繎1瓚婂ソ銆

❷ 1.2344鏄浠涔堟潗鏂

1.2344妯″叿閽㈡潗鏂欎粙緇

鎶氶『鐗歸挗1.2344

1.2344浣滀負閾濄侀攲鍘嬮摳妯″叿鏉愭枡鏃忚嬌錛屽簲鐢ㄦ渶涓哄箍娉涖1.2344鏄涓縐嶅己搴︾潄絀楄櫄銆侀煣鎬с佽愮儹鎬ц秼浜庡鉤琛＄殑鐑浣滄ā鍏烽挗銆傚洜鍚勫悜鍚屾у寲錛屼嬌鍏跺叿澶囬珮闊фх瓑鏂瑰悜鎬э紝浠庤屾彁楂樹簡妯″叿瀵垮懡錛屾ц兘鏇寸ǔ瀹氥

鎶氶『鐗歸挗1.2344妯″叿閽㈠瑰簲鐗屽彿

濂ュ湴鍒╋細W302 寰峰浗錛1.2344 鏃ユ湰錛歋KD61 緹庡浗鎮夌噧錛欻13 鐟炲吀錛8407

1.2344妯″叿閽渚涘簲鐘舵

閫鐏錛屸墹259HB

1.2344妯″叿閽㈢敤閫

閫氬父鐢ㄤ簬閾濋摳浠剁敤鐨勫帇閾告ā錛岀儹鎸ゅ帇妯★紝絀垮瓟鐢ㄧ殑宸ュ叿銆佽姱媯掋佸帇鏈洪敾妯★紱濉戞枡鑶滅瓑錛岃繕 騫挎硾搴旂敤浜庨摑銆侀摐鍙婂叾鍚堥噾鐨勫帇閾告ā鍏楓

❸ 姘╁姬鐒婄殑鍩虹鐭ヨ瘑

鍩虹鐭ヨ瘑瑙佷笅闈錛
姘╁姬鐒婅殏琛鎶鏈鏄鍦ㄦ櫘閫氱數寮х剨鐨勫師鐞嗙殑鍩虹涓婏紝鍒╃敤姘╂皵瀵歸噾灞炵剨鏉愮殑淇濇姢錛岄氳繃楂樼數嫻佷嬌鐒婃潗鍦ㄨ鐒婂熀鏉愪笂鋙嶅寲娓楁媶鎴愭恫鎬佸艦鎴愮啍奼狅紝浣胯鐒婇噾灞炲拰鐒婃潗杈懼埌鍐墮噾緇撳悎鐨勪竴縐嶇剨鎺ユ妧鏈銆
闈炵啍鍖栨癌寮х剨鏄鎸囩數寮у湪鐔斿寲鏋(閫氬父涓洪挩鐢墊瀬)涓庡伐浠朵箣闂寸噧鐑э紝鍦ㄧ剨鎺ョ數寮у懆鍥撮氳繃涓縐嶆儼鎬ф皵浣(姘)甯哥敤錛屼笉涓庨噾灞炲彂鐢熷弽搴旓紝褰㈡垚淇濇姢濂楃★紝浣塊挩鏋併佺數寮у拰鐔旀睜涓庨搧姘翠笉鏆撮湶浜庣┖姘斾腑錛屽彲闃叉㈡湁瀹充笡鐗╂灒姘斾綋鐨勬哀鍖栧惛鏀躲